Single supply voltage: 1.65 V to 3.6 V
Max clock frequency: 5 MHz
Serial Peripheral Interface (SPI) Compatible
Standard SPI: C, S#, D, Q, W#, HOLD#
Write
Byte/Page Write within 5ms
Additional Write lockable page (Identification Page)
Additional 128 bits Serial Number (Unique ID)
Hardware Controlled Locking of Protected Sectors by WP Pin
Transparent ECC on each group of four bytes which can correct 1-bit error
Reliability
Endurance:
1 Million Write Cycles
Data Retention:
100 Years
Package: PDIP8,SOP8(150mil/208mil),MSOP8,TSSOP8,UDFN8
1.3 Signal Description
During all operations, VCC must keep stable and within the specified valid range: VCC(min) to VCC(max).
All of the input and output signals must keep high or low according to voltages of VIH, VOH, VIL or VOL, as
specified in: DC and AC parameters. These signals are described next.
1.3.1 Serial Data Output (Q)
This output signal is used to transmit data sequentially into the device. Data is shifted out on the falling edge
of Serial Clock (C).P25C256F Datasheet Rev. 1.1
Puya Semiconductor
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1.3.2 Serial Data Input (D)
This output signal is used to transmit data sequentially into the device. It receives instructions, addresses, and
the data to be recorded. Values are latched on the rising edge of Serial Clock (C).
1.3.3 Serial Clock (C)
This input signal provides the serial interface timing. The instructions, addresses, or data present in the Serial
Data Input (D) are glued on the rising edge of Serial Clock (C). The data on the Serial Data Output (Q)
changes at the lower edge of Serial Clock (C).
1.3.4 Chip Select (S#)
During the signal is high, the device is deselected and Serial Data Output (Q) is at high impedance. The
device will be in the Standby mode, only when an internal Write cycle is in progress. Driving Chip Select (S#)
low selects the device, placing it in the Active Power mode.
After power-up, a falling edge on Chip Select (S#) is required before beginning instruction.
1.3.5 Hold (HOLD#)
The Hold (HOLD#) signal is used to pause any serial communications with the device without deselecting the
device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial
Clock (C) are Don’t Care.
To start the Hold condition, you must select the device, and at the bottom of Chip Select (S#).
1.3.6 Write Protect (W#)
The main purpose of this input signal is to freeze the size of the area of memory that is protected against
Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register).
This pin must be driven either high or low, and must be stable during all Write instructions.
1.3.7 VCC supply voltage
VCC is the supply voltage.
1.3.8 Vss ground
Vss is the benchmark for all signals, including voltage supply Vcc.
